1. Field of the Invention
The present invention generally relates to highly conformal extension doping in advanced multi-gate devices, and, more particularly, to the formation of highly conformal source/drain extension regions close to a channel of advanced multi-gate devices.
2. Description of the Related Art
The majority of present-day integrated circuits (ICs) are implemented by using a plurality of interconnected field effect transistors (FETs), also called metal oxide semiconductor field effect transistors (MOSFETs) or simply MOS transistors. Typically, present-day ICs are implemented by millions of MOSFETs formed in or on a semiconductor material provided on a substrate with a given surface area.
The basic function of a MOSFET is that of an electronic switching element, wherein a current through a channel between source and drain of a MOSFET is controlled by a gate to which a voltage is applied. Particularly, the conductivity state of a MOSFET is changed when applying a voltage to the gate such that the applied voltage passes a certain voltage value, usually referred to as threshold voltage (Vt). The switching behavior of a MOSFET is, therefore, substantially characterized by the value of Vt. In general, Vt depends nontrivially on the transistor's properties, such as gate materials, etc., and is, e.g., very sensitive to the concentration of dopants in the channel, drain and source.
Progress in semiconductor techniques has steadily led to increasing integration densities and decreasing sizes of semiconductor devices and semiconductor device features. For example, efforts have been made to develop faster ICs by reducing the length of gate electrodes in MOSFETs and accordingly achieving smaller channel lengths. As a result, conventional fabrication techniques have been pushed to their limits, challenging the abilities to produce finely defined features at presently-required scales reaching deep into the nanometer regime.
In order to circumvent challenges encountered in scaling current MOSFETs, recent approaches have been directed away from fabricating MOSFETs having a gate electrode overlying a two-dimensional or planar surface of a semiconductor material (planar MOSFET) towards MOSFET configurations in which the gate electrode is formed on a substantially non-planar surface of a semiconductor material. An example of such a non-planar configuration is given by a finFET where a fin is formed in or on a surface of a semiconductor material and the gate electrode overlies the fin such that a conducting channel within the fin is partially enclosed by the gate electrode covering the fin at more than one face as opposed to planar MOSFET configurations. In comparison to planar MOSFET configurations, the drive current capability and control of the conductivity of a channel is improved in non-planar MOSFET configurations.
In advanced semiconductor manufacturing techniques, independent from whether planar or non-planar configurations are implemented, conformal doping is a key issue because a MOSFET's performance crucially depends on how exactly required parameters are implemented during fabrication, particularly in advanced semiconductor devices where even small deviations from target values result in undue shifts in parameters in properties to be realized. For example, it is very important to form source/drain extension regions with a well-defined gate overlap and a good abruptness of the doping profiles so as to reproducibly implement a desired and required length of the channel region extending between source/drain regions. It is easy to see that deviations in the gate overlap and the abruptness of the doping profiles of source/drain extension regions have an increasing impact on the resulting length of a channel when reaching presently advanced technology nodes at 35 nm or smaller. Implantations of source/drain extension regions at advanced technology nodes do not satisfy conformity requirements at high doping levels.
U.S. Patent Publication No. 2004/0104442 shows a planar MOSFET configuration in which source/drain extension regions are formed by depositing a doped high-k material layer over a gate electrode and applying a thermal annealing process at an annealing temperature between about 800-1200° C. for an annealing time of 10 seconds to 30 minutes in order to diffuse dopants incorporated into a dielectric material of sidewall spacers into underlying extension regions without implanting the dopants into the extension regions.
However, incorporating deposition processes and diffusion processes into existing process flows is not a straightforward task as each change of established process flows may unexpectedly affect subsequent processing, as changing or replacing established process sequences and including additional diffusion causing sequences is likely to considerably change characteristics of devices under fabrication in such a way that process parameters of subsequent processes have to be adjusted anew in order to implement required device characteristics. In summary, deviations of established process flows hold a number of drawbacks affecting performance and reliability of devices under fabrication, such as increasing integration complexity and increasing thermal budgets.
It is, therefore, desirable to provide highly-conformal source/drain extension regions in semiconductor devices having non-planar configurations.